Shared search
Silicon design or verification engineers who worked at Intel DCAI in Santa Clara in the last two years, senior IC level, currently in the Bay Area.
4 results across 4 people
1
Pratik Mahajan28y exp
Engineering Leader in Formal Verification | Formal COE @Intel
San Francisco Bay Area· 1y at co.
2
John Pratheep Kulanthai Samy25y exp
at Marvell Technology | World’s First 5G Chip at Intel | First HoloLens Product at Microsoft | First NFC product at ST-Ericsson | Unique Combination of Functional, Formal and Low Power Verification Leadership |
San Francisco Bay AreaRecently started
3
Lata Jindal32y exp
Al Silicon @ intel
San Francisco Bay AreaRecently started
4
Vishal Chandrasekhar16y exp
Staff Silicon Packaging Architect at Intel Corporation |
Master’s in Mechanical Engineering
San Francisco Bay Area· 2y at co.Possibly open
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