Shared search
Senior RTL or physical design engineers currently at Intel in Hillsboro, Chandler, or Fort Collins with Xeon or server CPU experience
35 results across 35 people
1
Rashid Hameed19y exp
Physical Design (Xeon) @Intel | Berkeley MBA
San Francisco, California, United States· 5y at co.Likely open
English (Native or bilingual proficiency)Urdu (Native or bilingual proficiency)Integrated Circuit DesignASIC+18
2
Nikhil Saxena26y exp
Transforming Visions into Silicon Realities | Director of Engineering with 25 Years in Physical Design: Xeon Servers , ASICs, CPU Cores, Automotive Chips, and 3D SOCs in Graphics Domain
Greater Bengaluru Area· 1y at co.
Continuous Improvement3DICEnd to End Physical Design3D SOC+14
3
Anthony Bouchard26y exp
Director of Engineering, Xeon Server at Intel Corporation
Fort Collins, Colorado, United States· 5y at co.Possibly open
4
Tiju Jacob23y exp
Principal Engineer at Intel Corporation
Hillsboro, Oregon, United States· 4y at co.
Physical DesignCPU designEngineeringIntegrated Circuit Design+16
5
LS
Luke Soasey29y exp
Principal Engineer at Intel Corporation | 28 years of experience in leading edge microprocessor design | Currently specializing in post-silicon debug microarchitecture for Intel's Xeon server CPUs
Fort Collins, Colorado, United States· 29y at co.Possibly open
Semiconductor EngineeringVery-Large-Scale Integration (VLSI)Technical LeadershipDFx Architecture / Microarchitecture+16
6
Ramalinga Reddy Kotapati17y exp
Chip Design Engineer at INTEL | IEEE Senior Member
Hillsboro, Oregon, United States· 1y at co.
Technology LeadershipTechnical Project LeadershipPlace & RouteSemiconductor Industry+3
7
Ganessh Balaji Chandrasekaran19y exp
SOC RTL Lead, DDG, Intel Corporation
Hillsboro, Oregon, United States· 6y at co.Likely open
EnglishTamilTeluguRTL design+19
8
Jimin Zhang14y exp
CLK RTL and uArch Lead
Hillsboro, Oregon, United States· 4y at co.
CDCSynopsys DC/ICC/PrimeTimeVHDLElectrical Engineering+9
9
Karthik Rajavel11y exp
Senior Physical Design Engineer
Hillsboro, Oregon, United States· 1y at co.
English (Full professional proficiency)Tamil (Full professional proficiency)Place & RouteVCLP+18
10
Amruta Desai19y exp
SoC Physical Design Domain Lead at Intel Corporation
Hillsboro, Oregon, United States· 4y at co.Possibly open
Coaching & MentoringCross-functional CoordinationConcept DevelopmentResource Management+16
11
Kawsher Ahmed Roxy10y exp
Sr. Physical Design CAD Engineer | Ph.D. in Electrical Engineering
Hillsboro, Oregon, United States· 5y at co.Likely open
English (Professional working proficiency)Digital Circuit DesignApplication-Specific Integrated Circuits (ASIC)Analog Circuit Design+17
12
Hemanth Kumar Tadikonda6y exp
Intel Corporation
Hillsboro, Oregon, United States· 3y at co.Likely open
English
13
Hai Ming Khor26y exp
IP Logic/RTL Design Engineer at Intel Corporation
Hillsboro, Oregon, United States· 20y at co.Likely open
English (Professional working proficiency)Mandarin (Professional working proficiency)Microarchitecture and RTL developmentHardware C Model development for verification+18
14
KL
Kevin Law32y exp
Senior Mask Designer / Physical Design Automation
Hillsboro, Oregon, United States· 32y at co.
CantoneseEnglish
15
Molly Olson44y exp
Director of Engineering Xeon + FPGA at Intel Corporation
Portland, Oregon, United StatesRecently started
EnglishIntelBusiness ProcessStrategic Planning+13
16
Bahaa Fahim25y exp
Intel Fellow | Xeon Chief Engineer and Architect at Intel Corporation
Santa Clara, California, United States· 4y at co.
VerilogASICEmbedded SystemsSemiconductors+13
17
MC
Muntaquim Chowdhury34y exp
Chief Xeon Architect, Intel Fellow
Bellevue, Washington, United States· 4y at co.Likely open
English (Native or bilingual proficiency)Russian (Native or bilingual proficiency)MicroarchitectureRTL design+23
18
Sheik Ashrub Mohammed25y exp
Senior Principal Engineer / Xeon Chief Engineer
San Jose, California, United States· 10y at co.Likely open
ASICCache CoherencyMicroprocessorsCPU design+12
19
Stephen Thomas12y exp
Intel® Xeon® Platform Applications Engineering Director at Intel Corporation
Portland, Oregon, United StatesRecently started
20
Jaywant Padval30y exp
Director - IP/ DFX/ Test Chip for Xeon CPU
Bengaluru, Karnataka, India· 7y at co.Likely open
Digital DesignsP&L ManagementStrategic PlanningTeam Leadership+9
21
Ivan Rojas13y exp
Xeon SoC Design Verification Engineer at Intel Corporation
Folsom, California, United StatesRecently started
English (Professional working proficiency)Spanish (Native or bilingual proficiency)Functional VerificationSystemVerilog+18
22
Jeffrey Chamberlain28y exp
Lead Xeon Fabric Architect
San Francisco Bay Area· 4y at co.Likely open
EnglishComputer ArchitectureDebuggingSoC+16
23
Raghuraman Ganesan25y exp
Principal Engineer & Director, AI Accelerators and Xeon Power/Performance/Binsplit Modeling at Intel Corporation
San Jose, California, United States· 5y at co.
Power and Performance ModelingApplication-Specific Integrated Circuits (ASIC)Very-Large-Scale Integration (VLSI)Semiconductors+12
24
Allan Muñoz31y exp
Sr. Director Xeon Validation at Intel Corporation
Austin, Texas, United States· 4y at co.Likely open
SpanishSemiconductorsProduct Lifecycle ManagementProduct Management+17
25
Arturo Morales34y exp
Senior Director, Xeon Silicon Validation Leader
United States· 10y at co.Likely open
EnglishSpanishSemiconductorsSoC+18
Ganapathy Kasturirangan26y exp
Senior Director - Technical Program Management, Xeon-D Servers at Intel Corporation
Bengaluru, Karnataka, India· 6y at co.Likely open
Static Timing AnalysisPlace & RouteFormal VerificationRTL design+11
Priya Sekar22y exp
Engineering Director @Intel Xeon Server Platform validation |Mentor|Technologist
Bengaluru, Karnataka, India· 1y at co.
EnglishHindiKannadaTamil+20
Sadaf Haseeb Khan25y exp
Senior Director, Xeon Server Engineering, Data Center Group at Intel Corporation
Santa Clara, California, United States· 4y at co.Likely open
SoC Design & ArchitectureStrategic Technical LeadershipGlobal Team ManagementPre-Silicon Validation & Emulation+16
abhishek kumar18y exp
SoC Security lead -Intel NEX Xeon & Networking Eng
Bengaluru, Karnataka, India· 1y at co.
pythonAIXUnixStorage Area Networks+41
Suresh Krishnasamy25y exp
Analog&Mixed Signal Electrical Architect |SI-PI-EMC/RFI IP/SOC/Chiplet/PKG@Intel Server and Client(Xeon CPU, GPU, XPU)| AI |Ex. Huawei China|Ex. Microsoft China |Ex. Nokia China |Ex. Honeywell USA |Ex. CDOT India
Bengaluru, Karnataka, India· 2y at co.
English (Native or bilingual proficiency)Systems EngineeringKeysight ADSAnalytical Skills+17
Akram Hassanien, M.E.21y exp
Director | Cloud RAN AI Product, GTM, Customer Success | Scaling $1B+ Xeon Telco RAN | Network & Edge Infrastructure & Ecosystems | x-Qualcomm | x-Ericsson
Plano, Texas, United States· 1y at co.
ArabicProgram ManagementPresentationsMulti-functional+55
Jayakumar Athinarayanasamy22y exp
Technical Lead - Xeon Platform Validation and Debug at Intel Corporation
Bengaluru, Karnataka, India· 3y at co.Possibly open
Technical LeadershipInfluenceMentoringPath Finding+7
FL
Felix Leung31y exp
Sustainability & Energy Efficiency Product Management - Xeon Platform
Portland, Oregon, United States· 4y at co.Likely open
English (Native or bilingual proficiency)Cantonese (Native or bilingual proficiency)Mandarin (Native or bilingual proficiency)Japanese (Elementary proficiency)+66
SN
Surya N.8y exp
Staff Engineer - CPU Performance & Design Verification for Xeon AI Processor
United States· 5y at co.Likely open
EnglishVerilogUVMSystemVerilog+4
Yi Ding29y exp
General Manager, Xeon Program Office at Intel Corporation
San Francisco Bay Area· 3y at co.Likely open
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