Etched Just Hit $10.3B. The US ASIC Pool Meta Already Owns.

On July 23, 2026, Etched closed a $300M Series C led by Sequoia at a $10.3B valuation, doubling its price in seven months and putting a 35-person company into direct hiring competition with NVIDIA, Broadcom, and Groq. The hard part isn't the money. The hard part is that the US pool of engineers who can actually tape out a transformer-only ASIC fits in a mid-sized conference room.

If you run hiring at an inference-hardware startup, the next 90 days decide whether you get a founding RTL hire or spend Q4 losing bake-offs to a company with a $294M valuation-per-employee war chest.

What Etched actually raised, and why the hiring math changed overnight

Etched raised $300M at a $10.3B valuation on July 23, 2026, in the highest-valued Sequoia-led Series C ever, less than a month after formally emerging from stealth. The round was led by Sonya Huang at Sequoia, with a16z, Jane Street, Diffusion, and SK Hynix participating, and it takes total funding to roughly $800M.

The relevant numbers for anyone else trying to hire in this space:

• $10.3B post-money, up from $5B in December 2025 (2.06x in seven months).
• ~35 employees pre-Series C, per startupintros.com.
• ~$294M valuation per employee, versus roughly $70M to $100M per employee at NVIDIA.
• $1B+ in signed customer contracts, with A0 silicon back from TSMC N4P and first racks moving toward shipment.

That valuation-per-employee ratio isn't a vanity metric. It's the cash envelope Gavin Uberti (CEO), Rob Wachen (president), and Chris Zhu (CTO) can offer a senior RTL designer without diluting past the point of investor comfort. Any competing offer from a Series A or B inference-chip startup is now getting benchmarked against that number, whether the candidate says so or not.

$294M

How thin is the US transformer-ASIC pool, really

The pool of US engineers currently titled ASIC Design Engineer, RTL Design Engineer, Senior ASIC Engineer, or RTL Engineer is 909, and it is far more concentrated than the round-number suggests. In Refolk's index of professional profiles, queried in July 2026, the top-of-list employer isn't NVIDIA. It's Meta.

Two things fall out of that table that most sourcing teams get wrong.

First, filtering by the literal title "RTL Design Engineer" on LinkedIn will systematically underweight NVIDIA. NVIDIA titles most of its RTL work as GPU Architect, Design Verification, or Physical Design. If you use a Boolean string that leans on the RTL keyword, you'll conclude NVIDIA has almost no relevant engineers and set your comp bands too low. It has plenty. They just don't say "RTL" on the tin.

Second, the transformer-literate subset of these 909 is much smaller than 909. When you cross ASIC/RTL titles with skill tags for Transformer, MHA, or KV-cache, structured filters return effectively zero, because that literacy lives in profile free-text and project descriptions, not skill chips. Realistic estimates put the true intersection well under 50 people in the US, which is why every one of these hires becomes a named search.

This is the exact gap Refolk closes for hardware recruiters: instead of building a 200-token Boolean string that misses NVIDIA and Broadcom entirely, you describe the person in plain English ("US RTL designers who mention attention, KV-cache, or transformer inference anywhere in their profile") and get a ranked shortlist that reads the free-text the way a human would.

Why Meta's MTIA is the highest-yield poach target, not NVIDIA

Meta's MTIA org is the single largest concentration of poachable ASIC design engineers in the US pool, and unlike NVIDIA it doesn't have retention-locked options priced at NVIDIA-2026 stock levels. That's a structural gift to any transformer-ASIC startup hiring right now.

The mechanism has three parts:

1. Concentration. 13 of the top-10-employer sample sit at Meta, more than 4x Apple's count and more than the entire NVIDIA-titled RTL population in the same sample.
2. Retention math. NVIDIA RSUs granted in 2023 or 2024 have appreciated so violently that any lateral move requires a signing bonus in the mid six figures just to break even. Meta grants from the same window are underwater relative to that curve.
3. Roadmap ambiguity. MTIA v1 and v2 shipped, but the org's next-gen direction has been publicly quieter than TPU or Trainium, which reads to senior ICs as career risk.

Etched has already exploited this. The company has publicly recruited from Intel, Broadcom, Tesla, Google, and Meta, and its early RTL bench leans on people who shipped domain-specific silicon (TPU, Tesla FSD, Broadcom custom ASICs), not GPU generalists. The reason is architectural conviction: Sohu is a bet-the-tape-out design where the entire silicon flow, fabrics, interconnects, math blocks, and memories, is custom for one workload. You want engineers who've made that kind of bet before and shipped.

The scarce skill isn't RTL. It's RTL plus the willingness to bet a tape-out on a specific attention variant.

The Cypress alumni nobody is bidding on

The single most under-priced pool for inference-ASIC hiring right now is Cypress Semiconductor alumni (now inside Infineon), because they combine mixed-signal and memory-controller RTL depth with zero AI-recruiter visibility. Etched already figured this out and has been quietly hiring senior engineers from Cypress and Broadcom alongside its higher-profile Meta and Google poaches.

Why Cypress maps onto Sohu specifically:

• Memory-controller depth. Sohu is a cluster-scale inference part where HBM bandwidth and on-chip SRAM hierarchy dominate the design. Cypress veterans spent careers on exactly this class of problem for embedded and networking silicon.
• Low-voltage discipline. Transformer inference at rack scale is a power-envelope fight. Mixed-signal RTL designers understand voltage domains and clock trees the way pure GPU folks do not.
• No AI-recruiter competition. Cypress is not on any AI-hiring dashboard. There is no LinkedIn Recruiter saved search that surfaces these people alongside your usual NVIDIA/Broadcom pulls.

Adjacent under-priced pools worth naming:

• Tesla Dojo alumni post the 2024 wind-down, particularly those with SerDes and interconnect experience.
• Amazon Annapurna Labs / Trainium designers in Austin, which shows up as a secondary cluster in Refolk's regional distribution after the South Bay.
• Intel Xeon RTL designers exiting the recent divisional cuts, who bring server-class validation rigor.

The pitch that beats a $294M-per-employee cash offer

You don't beat Etched on cash. You beat Etched on architectural optionality, by offering RTL work that isn't locked to a single model family. That is the single most effective sourcing pitch to senior transformer-ASIC candidates in 2026.

The reason is a fear Etched's own skeptics keep voicing: something like 1.5-bit transformers, or a post-attention architecture, could obsolete a transformer-only ASIC in six months. The same fear that applies to Sohu the product applies to Sohu the career. A senior RTL designer who takes an Etched offer is betting their next four years on the current attention formulation surviving one more architecture cycle.

Startups sourcing against Etched should structure the pitch as:

• Dual-path scope. RTL plus compiler, or RTL plus microarchitecture research, so the candidate's next role isn't locked to one dataflow.
• Named workload diversity. Explicitly list two or three workload classes (transformer inference, diffusion, recommendation) the silicon will target, even if transformer is the near-term priority.
• Publication and patent freedom. Etched's IP posture is closed by necessity. Smaller startups can offer publication rights on non-core blocks, which matters more to this pool than most recruiters realize.
• Relocation reality. 14 of the top-25 US sample sit in Santa Clara, San Jose, and Sunnyvale. If you're hiring outside the Bay, budget 3 to 6 months of non-compete cooldown plus relocation, or plan to open a South Bay satellite.

909

A 30-day sourcing plan for founders competing with Etched

Run three parallel workstreams for the next 30 days, because the compensation floor for this pool will reset before Q4 and every week of delay compounds. Here is the sequence that actually works when the target pool is under 50 humans.

Week 1: map the named 50

Build a single named list of every US RTL designer with visible transformer, attention, or KV-cache evidence in their profile or GitHub. Do not use Boolean. Use a plain-English query against a search layer that reads free-text, which is exactly what Refolk was built for. Tag each profile with current employer, tenure, and last vesting cliff estimate.

Week 2: warm-intro mapping

For each of the 50, identify one warm-intro node. Andrej Karpathy is a named investor in Etched and is a hub for transformer-literate researchers considering hardware; the same graph works in reverse for competitors. Sonya Huang, Peter Thiel, Dylan Field, and Amjad Masad are all in the Etched cap table and adjacent to the same talent graph.

Week 3: first messages, sequenced by pool

Send different first messages to different pools:

• Meta MTIA: lead with roadmap clarity and publication rights.
• NVIDIA (by architect/DV title, not RTL): lead with dual-path scope and IPO-timeline honesty.
• Cypress/Infineon: lead with the memory-controller and low-voltage angle, because they've been ignored by AI recruiters for two years.
• Tesla Dojo and Intel Xeon RTL: lead with team seniority and tape-out cadence.

Week 4: onsite compression

Compress the loop to two weeks from first message to offer. Etched's 35-person team can move fast; a slower loop is how you lose a candidate you already convinced. This is the discipline most Series A hardware startups underinvest in, and it is the single biggest lever after sourcing itself.

FAQ

How many US engineers can actually design a transformer ASIC today?

The total US pool of ASIC/RTL Design Engineers is 909 in Refolk's index, but the transformer-literate subset (engineers who cite attention, MHA, or KV-cache in their profile evidence) is realistically under 50. Structured skill-tag filters return effectively zero, which means every real search on this pool is a named search built from free-text evidence, not a Boolean string.

Why is Meta a better poach target than NVIDIA for inference-chip startups?

Meta's MTIA org holds the largest single concentration of ASIC design engineers in Refolk's US top-10 sample (13, versus a NVIDIA count of 1 by literal title). NVIDIA also carries retention-locked RSU packages from 2023 and 2024 grants that require mid-six-figure signing bonuses just to make a candidate whole, while Meta grants from the same window sit closer to at-the-money.

What's the fastest way to source this pool without competing with Etched head-on?

Target adjacent pools that AI recruiters ignore: Cypress/Infineon alumni for memory-controller and mixed-signal depth, Tesla Dojo alumni post the 2024 wind-down, and Amazon Annapurna/Trainium designers in Austin. Etched has already been hiring from Cypress and Broadcom precisely because those names don't trigger bidding wars. A plain-English query in Refolk surfaces these people faster than Boolean, because the relevant experience sits in project descriptions rather than skill tags.

How should I structure comp against a $294M-per-employee competitor?

Don't try to match cash. Structure against Etched's single biggest recruiting liability, which is architectural lock-in to one attention formulation. Offer dual-path scope (RTL plus compiler, or RTL plus microarchitecture research), named workload diversity beyond transformers, publication rights on non-core blocks, and honest IPO-timeline framing. This pool has watched enough architecture cycles to price optionality over base salary.