AMD Data Center Hit $6.7B. The US Senior ROCm Pool Is 37.

AMD reported Q2 2026 revenue of $11.5B, up 50% year-over-year, with Data Center more than doubling to $6.7B. Within a week, enterprise ML infra job descriptions started adding "ROCm/HIP experience required," and the global population of engineers who have actually shipped ROCm code is roughly four orders of magnitude smaller than the CUDA pool.

This is a sourcing playbook for a market that is not really a market yet. If you are writing a JD off the back of AMD's momentum, you need to know exactly who exists, where they sit, and which signal to trust before you burn a quarter chasing ghosts on LinkedIn.

The pool is 224 globally, 37 in the US senior tier

In Refolk's index, 224 people worldwide list both ROCm and HIP as declared skills. Filter to Senior+ titles in the US and it collapses to 37. For context, 40,056 professionals list CUDA. That is a 179x gap between the incumbent stack and the challenger, and it exists ten years after ROCm's first release in November 2016.

The 179x figure understates the true gap because Nvidia's own count is 5 million CUDA developers as of June 2024, up from 2 million in 2020. Registration is not required to download the CUDA toolkit, so 5M is a conservative floor. The ROCm side has no equivalent claim, and the ROCm/HIP GitHub repo sits at 4.2k stars and 574 forks. That is the total addressable universe you are recruiting against.

179x

AMD is holding 16% of its own US senior pool

Six of the 37 US senior ROCm/HIP engineers already work at AMD. The next-largest concentrations are one each at Oracle, Intel, Meta, and Microsoft, per Refolk's index. If AMD ramps hiring into H2 to match its Q3 guide of $12.7B to $13.3B, every other buyer is competing over a pool of roughly 31 people, most of them clustered in the Bay Area, NYC, Austin, and Greater Seattle. That is not a market. That is a Rolodex.

The mechanism matters. AMD is both the largest employer of ROCm-native engineers and the primary trainer of new ones. Hyperscalers stand up MI300X clusters - Oracle Cloud Infrastructure is the clearest example - and then poach from Santa Clara. If you are recruiting for a Series B ML infra startup, you are third in line behind AMD retention offers and OCI's compensation bands.

Every one of the 37 has a LinkedIn profile. What LinkedIn will not tell you is who among them has actually merged a PR into ROCm/TheRock in the last six months, which is the only skill signal that matters for a real ROCm hire. That is the exact gap Refolk closes: describe the person in plain English ("US senior engineer with recent ROCm/TheRock or hipBLASLt commits, not currently at AMD") and get a ranked shortlist with the GitHub evidence attached.

"ROCm engineer" is usually a mislabel for "porting engineer"

Most enterprises writing ROCm/HIP into requisitions do not need someone to build ROCm primitives. They need someone to port an existing CUDA codebase to AMD hardware, which is a fundamentally different job. HIP is a C++ runtime API and kernel language for AMD GPUs that mirrors CUDA closely enough that most CUDA code can be mechanically translated. The porting path is the product.

This reframes the sourceable pool dramatically. If your real requirement is "can read CUDA, willing to learn HIP, comfortable with LLVM toolchains," you are recruiting against a slice of the 40,056 CUDA-declared population, not the 224 ROCm-declared one. The right JD does not say "10 years ROCm experience," because that candidate does not exist. ROCm 1.0 shipped November 14, 2016, and stable release 7.2.4 landed May 29, 2026. The theoretical maximum is nine and a half years.

A defensible JD looks more like this:

• Ships CUDA kernels in production, with public evidence
• Has read or contributed to HIP, ROCm/TheRock, hipBLASLt, or PyTorch's AMD backend
• Comfortable in LLVM/MLIR or GPU compiler internals
• Bonus: has stress-tested AMD hardware on tinygrad, MLC-LLM, or vLLM

The maximum plausible "10 YoE ROCm" candidate literally does not exist yet. ROCm is nine and a half years old.

The GPU compiler engineer shortage is worse than the ROCm shortage

The binding constraint is not ROCm knowledge. It is LLVM/AMDGPU backend fluency, and that pool is smaller and more concentrated than the ROCm one. ROCm's compiler toolchain is HIPCC, an LLVM-based compiler. If your role touches kernel codegen, autotuning, or graph compilers, you are recruiting compiler engineers who happen to know AMDGPU targets, not ML engineers who happen to have installed ROCm.

The named concentrations for this profile are narrow:

1. AMD's own compiler team
2. Modular, building the MAX/Mojo compiler stack
3. Academic HPC labs working on AMD systems
4. SCALE (scale-lang.com), a startup building a CUDA toolchain that compiles to non-Nvidia GPUs
5. tinygrad / tinycorp, which has publicly stress-tested AMD's stack on the 7900 XTX and MI300

Write the JD for LLVM/MLIR contributors with GPU targets, not for "ROCm engineers." You will get a strictly larger and more qualified funnel, and you will stop competing head-to-head with AMD's own retention team over the same six names.

Where to source: five GitHub signals that beat LinkedIn

Stop searching LinkedIn for "ROCm." Start with the repos where contribution is proof, not self-declaration. Five signals, in order of quality:

1. ROCm/TheRock contributors. TheRock is a lightweight open source build platform for HIP and ROCm with nightly releases of ROCm and PyTorch and a CMake super-project for source builds. Active contributors here are elite; the barrier to a merged PR is high.
2. ROCm/HIP repo PR authors. 4.2k stars, 574 forks. Small enough that every merged non-AMD PR is a named lead.
3. hipBLASLt and rocBLAS. The BLAS-level primitives; contributors are the people who can write and tune kernels, not just consume them.
4. PyTorch, vLLM, and MLC-LLM PRs tagged AMD/ROCm. Cross-pollinators who ported major frameworks to AMD hardware. These profiles almost never show up in a "ROCm" LinkedIn search.
5. tinygrad AMD backend commits. George Hotz's team publicly benchmarks and debugs AMD firmware on the 7900 XTX and MI300. The contributor list is a shortlist for ROCm-fluent generalists.

The workflow that works: pull PR authors from those repos over the last 6 to 12 months, dedupe, cross-reference against employer (excluding AMD if you want net-new hires), and enrich with contact info. That is a two-day project done by hand, or a plain-English query in Refolk that runs across GitHub, LinkedIn, and the open web at once.

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The Helios and MI308 signals to front-run

Two forward hiring signals from AMD's Q2 call are worth watching before the JDs proliferate. Lisa Su cited the Helios rack-scale platform as an H2 driver, which means "Helios" will become a JD keyword through Q3 at hyperscalers building competing rack-scale offerings. Second, Data Center revenue more than doubled to $6.7B despite the China MI308 export ban; if an export-controlled variant gets approved, Instinct headcount plans will spike overnight. AMD shares fell 8.94% after hours to $472.20 despite the beat, which reads as impatience with the pace of AI ramps - the hiring pressure to accelerate that ramp is not going down.

Front-run both by sourcing now against forward-looking criteria:

• Rack-scale GPU networking experience for the Helios ramp
• Fleet-level GPU operations at MI300X scale, currently concentrated at OCI, Microsoft, and Meta
• Export-compliance-adjacent hardware experience for the MI308 approval scenario

The engineers who fit these criteria are not going to appear in a "ROCm" keyword search. They are going to appear in an "I need someone who has run MI300X clusters in production and can talk about rack-scale topology" search, which is the shape of query Refolk is built for.

The ex-AMD play is the real leverage

AMD is a net exporter of ROCm talent to hyperscalers as those teams stand up MI300X fleets. In Refolk's index, the non-AMD concentrations at Oracle, Intel, Meta, and Microsoft are individually tiny but collectively meaningful.

The tactical implication: your best sourceable pool is not "current ROCm engineers." It is:

• Ex-AMD engineers who left recently and know the stack cold
• Ex-Nvidia engineers who publicly ported code to AMD (SCALE, tinygrad, vLLM contributors)
• LLVM/AMDGPU backend contributors at academic HPC labs

Searching "ex-AMD" on LinkedIn returns thousands of irrelevant hits in sales, IT, and legal. The precision you need is "ex-AMD, senior, worked in ROCm or Instinct organizations, left recently, currently at a hyperscaler." That is a plain-English query with four filters, and resolving it by hand means writing four boolean strings and reconciling the results yourself.

FAQ

How many ROCm engineers exist globally?

In Refolk's index, 224 people worldwide list both ROCm and HIP as declared skills. That compares to 40,056 who list CUDA, a 179x gap. Nvidia itself claims 5 million CUDA developers as of June 2024, so the true gap on the developer side is closer to four orders of magnitude. The US senior slice of the ROCm/HIP pool is 37 people, of whom 6 already work at AMD.

Should I hire ROCm engineers or CUDA engineers who can port?

For most enterprise ROCm/HIP JDs, you need porting engineers, not ROCm-native ones. HIP is a C++ API designed to make CUDA code straightforward to translate to AMD hardware, so a strong CUDA engineer willing to learn the AMD toolchain is a valid hire. Reserve the "must have ROCm commits" bar for compiler, kernel, and framework-integration roles, where LLVM/AMDGPU expertise is genuinely rare.

Where do I find real ROCm contributors, not LinkedIn keyword matches?

Start with GitHub. The highest-signal repos are ROCm/TheRock, ROCm/HIP, hipBLASLt, and the AMD backend PRs in PyTorch, vLLM, MLC-LLM, and tinygrad. Merged PR authors in these repos are provably capable. Pull them, dedupe by employer, and prioritize non-AMD engineers if you want net-new hires. This is roughly a two-day manual project, or a single plain-English query in a sourcing tool that indexes GitHub commits alongside professional profiles.

Is the ROCm talent shortage temporary?

Directionally yes, but not on any timeline that helps 2026 hiring plans. ROCm shipped in November 2016, so the theoretical maximum is nine and a half years of experience, and the ecosystem only became commercially urgent with MI300X. The compiler and kernel talent pool grows slowly because it requires LLVM internals experience, which is itself a narrow specialization. The sourcing playbook above stays valid until that changes.