Shared search
US physical design or ASIC engineers currently at Nvidia, Meta, Apple, or Google, who have shipped a 5nm or smaller tape-out and are based within 40 miles of San Francisco.
25 results across 25 people
1
TH
Tiewen Han25y exp
Senior Silicon Engineering Leader | SoC & IP Development | Front-End Design | RTL Integration | Physical Design Collaboration | Engineering Management | Multiple Production Tape-outs
San Francisco Bay Area· 12y at co.Possibly open
2
JT
Jiapeng(Andy) Tang16y exp
SoC Physical Design Manager | Technical Lead at Apple
San Francisco Bay Area· 1y at co.
3
Srinivas Reddy Chirla18y exp
Engineering Manager at Apple | Physical Design | Silicon Engineering Group
San Francisco Bay Area· 6y at co.Likely open
4
Jaskirat (Jaski) Singh Bindra20y exp
Senior Physical Design Manager at Apple
San Francisco Bay Area· 1y at co.
5
Sumeet Aggarwal21y exp
SOC Physical design manager
San Francisco Bay Area· 6y at co.Possibly open
6
Rambabu Mandalapu19y exp
Principal Physical Design Engineer at Apple
San Francisco Bay Area· 6y at co.Likely open
7
Chao-Chun Liang15y exp
Physical design verification / physical verification / Bump RDL and padring design on advanced nodes
San Francisco Bay Area· 5y at co.Likely open
8
Karan Sabharwal8y exp
Hardware Engineer | Analog/Mixed-Signal Layout | ASIC Physical Design | Silicon Validation | Python Automation | Cadence Virtuoso, Calibre, Synopsys ICV
San Francisco Bay Area· 3y at co.Likely open
9
madhu namburi13y exp
ASIC Physical Design Engineer at Apple
San Francisco Bay Area· 6y at co.Likely open
10
Stanley Mathew11y exp
Senior Physical Design Verification Engineer at Apple | Ex-Siemens EDA
San Francisco Bay Area· 6y at co.Likely open
11
Chris Yong Il Lee25y exp
Senior Physical Design Engineer at Apple
San Francisco Bay Area· 6y at co.Likely open
12
Joao C.14y exp
Physical Design Methodology
San Francisco Bay Area· 7y at co.Possibly open
13
Harsh Patel9y exp
SoC Physical Design Engineer at Apple
San Francisco Bay Area· 6y at co.Likely open
14
Harpreet Kaur22y exp
Physical Design Engineer, STA at Apple
San Francisco Bay Area· 6y at co.Likely open
15
Ben Fahrenkrug10y exp
SoC Physical Design Engineer at Apple
San Francisco Bay Area· 3y at co.Likely open
16
Erik Luna6y exp
Physical Design Engineer, Stanford MS EE
San Francisco Bay Area· 2y at co.Likely open
17
Prince Kothadiya5y exp
Physical Design @ Apple | MS from Caltech
San Francisco Bay AreaRecently started
18
Chirag Wadhwani11y exp
Physical Design Engineer at Apple
San Francisco Bay Area· 5y at co.Likely open
19
Chien-Tang Hu14y exp
Physical Design Engineer at Apple
San Francisco Bay Area· 3y at co.Likely open
20
Sha Liu13y exp
Physical Design Engineer at Apple
San Francisco Bay Area· 7y at co.Possibly open
21
Trishit Dutta10y exp
Physical Design Engineer at Apple
San Francisco Bay Area· 3y at co.Likely open
22
Akshay Rajendraprasad13y exp
Physical Design Engineer at Apple
San Francisco Bay Area· 9y at co.Possibly open
23
Neeraja Rane13y exp
Physical Design Engineer at Apple
San Francisco Bay Area· 4y at co.Likely open
24
Ojas Pandav11y exp
Physical Design Engineer at Apple
San Francisco Bay Area· 7y at co.Likely open
25
Sai Venkata Kiran Makineedi10y exp
Physical Design Engineer at Apple
San Francisco Bay Area· 7y at co.Possibly open
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