Synopsys' Dec 16 Cut: 128 Engineers Against a 786-Person EDA Pool

Synopsys filed a WARN notice with the California EDD on August 31, 2026, four business days after posting the strongest quarter in its history. The filing eliminates 128 roles at 675 Almanor Avenue in Sunnyvale, effective December 16, and the national pool that competes for those engineers is smaller than most sourcing plans assume.

Why a record quarter produced a WARN filing

The 128 Sunnyvale cuts are Ansys integration math, not a demand problem. Synopsys' Q3 EDA revenue grew 8.5%, design IP grew 11% to $474 million, and total revenue climbed 42% year over year to $2.477 billion, with non-GAAP EPS of $3.91. CFO Shelagh Glaser flagged that the 8.5% EDA number came against a tough 16% Q3 '25 compare. Management raised fiscal 2026 revenue guidance to $9.69B to $9.74B and lifted free-cash-flow expectations to roughly $2.6 billion.

Five days later, the WARN dropped. The mechanism is the Ansys acquisition. When two large R&D orgs collapse into one, the cut list skews to duplicate function, not weak performers. That is a materially different candidate-quality signal than a stack-rank purge.

The board approved a broader restructuring plan in November 2025 for approximately 10% of the combined ~26,500-person workforce, with $300M to $350M in estimated costs, mostly severance, landing across fiscal 2026. The Sunnyvale filings are the visible tip:

• November 2025: 175 roles at Almanor Avenue
• March 2026: 55 roles
• August 31, 2026: 128 roles, effective December 16

Disclosed California total: 358 EDA and R&D engineers in ten months.

The national EDA pool is smaller than your ATS suggests

The U.S. pool of substitutes for a Synopsys physical-design or verification engineer is measured in the low thousands, not the tens of thousands most sourcing plans assume. In Refolk's index of professional profiles, the numbers look like this:

Read the two middle rows again. A single WARN filing puts ~4.7% of the entire national physical-design and verification IC pool onto the market in one geography on one day. If any meaningful share of the 128 are Staff or Principal, up to ~16% of the senior EDA IC layer in the U.S. becomes reachable.

786

The top current employers of the 2,742-person physical-design and DV pool, in order, are Intel, NVIDIA, Meta, Amazon, Ayar Labs, AMD Pensando, Cadence, Ampere, and Altera. The 786-person senior layer is concentrated at Intel, Synopsys itself, SambaNova, NVIDIA, Marvell, Samsung Semiconductor, and Siemens EDA. Those are the companies sourcing the same 128 names you are.

Geography compresses the fight, not the pool

Nearly half the national comparable pool sits within 30 miles of Almanor Avenue, which kills relocation drag and multiplies competition. San Jose is the #1 metro for the Physical Design and DV segment in Refolk's index, followed by Austin and the broader Bay Area.

For a Sunnyvale employer, that is a rare gift: no relocation package, no visa-transfer surprises for the visa-dependent share (Synopsys filed 64 LCAs for 1,683 positions in FY25-26), and no time-zone excuses. For a Boston or Austin employer, it is the opposite problem. You are asking a mid-career engineer who owns a house in Cupertino to consider a move at exactly the moment Intel, NVIDIA, Cadence, and Amazon Annapurna are offering onsite roles across the parking lot.

The tactical read: national recruiters should treat this WARN as a two-week window to pitch relocation before local offers arrive, not a four-month window ending on December 16.

The Dec 16 clock is hard, and peak responsiveness is not on Dec 16

The reachability window opens now and closes around mid-February, with peak reply rates two to four weeks after WARN filing, not on separation day. The filing lists the action as "Layoff Permanent," meaning no recall. Combine that with year-end RSU vest dynamics and, for visa-dependent engineers, the 60-day H-1B grace clock that starts on December 16, and the sequence compresses:

1. September 15 to October 15: highest reply rates. Engineers are processing the news, updating profiles, and taking calls before the holiday slowdown.
2. October 15 to November 30: interview-heavy window. Onsite loops with Intel, Cadence, and hyperscaler custom-silicon teams close here.
3. December 1 to December 20: offers and counter-offers. Signing bonuses spike as the H-1B 60-day clock becomes visible.
4. December 21 to February 15: the visa-dependent tail. Engineers who did not sign pre-separation are motivated but constrained by paperwork.

Recruiters who wait until the separation date to reach out are showing up on day 45 of a 60-day sprint. That is the exact gap Refolk closes for time-sensitive WARN sourcing: describe the person in plain English (for example, "physical design engineers in Sunnyvale who joined Synopsys via the Ansys acquisition") and get a ranked, name-level shortlist you can start emailing this week, not next month.

The sleeper pool nobody is tracking: Ansys R&D

The Sunnyvale WARN is the visible cut. The bigger, invisible one is Ansys R&D in Canonsburg, PA and Ann Arbor, MI, where multiphysics and CFD engineers are being reduced without triggering public WARN filings. State-level disclosure thresholds vary, and smaller batches slip under them.

Forum posts and LinkedIn activity from Synopsys and Ansys engineers point to reductions in Pennsylvania, Texas, and the Bay Area beyond what has been formally disclosed. If your product needs simulation, structural analysis, or CFD skills, this is the pool to build a name-level view of right now, because layoff trackers will never surface it.

Layoff trackers show WARN filings. They do not show the quiet cuts, which is where most ex-Ansys engineers actually live.

A sourcing tool that indexes profiles by employer, skill, and location rather than by public layoff feeds is the only way to see this population. A query like "R&D engineers at Ansys Canonsburg with Fluent or Mechanical experience" returns names whether or not a WARN was filed for them.

Survivor engineers are self-sourcing exits

The third round of Sunnyvale cuts changes what "reachable" means: current Synopsys employees are now nearly as responsive as WARN'd ones. Forum comments from inside the company read like this: "Most of the people with actual skills, the ones who could make a difference anywhere, are headed for the door."

That is not spin. When a company goes through three consecutive rounds at the same address over ten months, the survivors update their profiles regardless of whether their name is on the current list. Retention is worst among the exact senior EDA ICs you want most.

Practically:

• Do not restrict your outbound to confirmed WARN names. The 128 are public, but the reachable population at Almanor is larger.
• Reference the record quarter in your first message. It signals you understand the layoff is integration math, not a performance signal on the individual.
• Skip "sorry to hear" language for current employees who are not on the list. Pitch the role.

Where the 128 will actually land

Ten companies will absorb the majority of the 128, and half of them are hyperscaler custom-silicon teams that most EDA recruiters do not track as competitors. Based on the top current employers of the ex-Synopsys physical-design and verification population in Refolk's index:

• Direct competitors: Cadence, Siemens EDA
• Merchant silicon: Intel, NVIDIA, AMD Pensando, Marvell, Samsung Semiconductor, Ampere, Altera
• Hyperscaler custom silicon: Amazon (Annapurna, Trainium), Meta (MTIA), NVIDIA
• AI accelerator and photonics: SambaNova, Ayar Labs

The hyperscaler bucket is the one most EDA recruiters underweight. Amazon Annapurna is a persistent absorber of ex-Synopsys physical design talent. If you are a startup competing for the same 128, your comp benchmark is not Cadence, it is Meta MTIA.

4.7%

FAQ

When exactly do the 128 Synopsys engineers become available?

The WARN was filed August 31, 2026 and the separation date is December 16, 2026. Peak responsiveness runs from mid-September through late October, well before the separation date. Recruiters who wait until December 16 to start outreach are competing at the tail end of a sprint that Intel, Cadence, and Amazon Annapurna started in early September, when Aidin Vaziri broke the filing in the San Francisco Chronicle.

How is this different from the Nov 2025 and Mar 2026 Sunnyvale cuts?

It is the third round at 675 Almanor Avenue in ten months, following 175 roles in November 2025 and 55 in March 2026. Cumulative disclosed California cuts now total 358 EDA and R&D engineers. The compounding effect matters: survivor engineers are self-sourcing exits, so outbound to current Synopsys employees at Almanor is now nearly as productive as outbound to the WARN'd names.

Why does a record-revenue quarter produce layoffs?

The cuts are Ansys integration math, not a demand problem. Synopsys reported 42% year-over-year revenue growth and raised full-year guidance five days before filing the WARN. The board approved a ~10% workforce reduction in November 2025 to eliminate duplicate function from the merged org, with $300M to $350M in restructuring costs booked mostly in fiscal 2026. The 128 are being cut because their function overlapped with an Ansys counterpart, not because they underperformed.

How do I find the Ansys engineers that never appear on WARN trackers?

You need a profile-level index rather than a layoff feed, because sub-threshold cuts in Canonsburg, Ann Arbor, and Bay Area Ansys offices do not trigger public filings. A query like "R&D engineers at Ansys Canonsburg with CFD or multiphysics experience, updated LinkedIn in last 90 days" returns a name-level shortlist regardless of whether a WARN exists. This is the sleeper pool, and it is significantly larger than the disclosed 358.