Intel Cut 2,392 Oregon Fab Engineers. Only 3 Buyers Exist.

Intel's July 15, 2026 Oregon layoffs landed at 2,392 workers, roughly 4.5x the 530 the November 2025 WARN filing described. If you recruit for a leading-edge fab, this is the biggest single supply shock the U.S. semiconductor labor market has seen in a decade. It is also narrower than it looks: the roles Intel eliminated only transfer cleanly to three employers.

Why Intel's Oregon cuts are a fab-specific event, not a general tech layoff

The 2,392 are overwhelmingly manufacturing roles tied to a specific tool set, which is why standard tech-recruiter playbooks fail here. Nearly every headline in this round is a fab title:

• More than 400 module equipment technicians
• Over 300 module development engineers
• Nearly 150 module engineers
• A large but unenumerated block of process integration engineers
• Additional general manufacturing technicians across four Oregon campuses, including Ronler Acres and Aloha

Oregon is Intel's single largest global site at about 20,000 employees, so 2,392 is roughly 12% of the campus gone in one action. And unlike prior Intel rounds, there are no buyouts. These are straight eliminations with 60-day WARN windows closing now, which means candidates are on the market motivated and negotiating from weakness, not sitting on 6 to 12 months of severance runway.

The macro driver is Intel Foundry's $3 billion operating loss in Q2 2025 and CEO Lip-Bu Tan's target of shrinking global headcount from 108,900 to about 75,000, a 31% cut. Expect more Oregon rounds. Treat this one as the opening move.

The realistic buyer set is three fabs, not thirty

For advanced-node process integration and module development work, only TSMC Arizona, Samsung Austin/Taylor, and GlobalFoundries Malta can actually use these engineers in the roles they trained for. Everyone else on the "semiconductor employers" list is a distractor.

Here is why the buyer set collapses so fast:

• Micron runs memory (DRAM/NAND), not leading-edge logic. Process integration transfers poorly.
• Texas Instruments runs analog and mature nodes. Module development recipes on Intel's leading-edge nodes don't map.
• Wolfspeed is silicon carbide. Different physics entirely.
• Apple, Google, Meta silicon teams hire ex-fab engineers, but into architecture and design roles, not fab operations. That is a career switch, not a lateral.
• Applied Materials, Lam Research, ASML absorb displaced fab engineers into customer-facing field roles. Useful exit ramp, but not "fab engineer hiring" in the strict sense.

That leaves the three named fabs. TSMC Arizona is already running an open onsite hiring event in Phoenix specifically for equipment, process, and manufacturing technicians, framed by TSMC as "a hiring event and not a career fair." Samsung Austin's Advanced Node Process Integration team is explicitly scoped to "14nm and beyond products in a high volume production environment." KORE1's analysis names GlobalFoundries Malta as the third destination. That is the buyer list.

What Refolk's index says about the actual pool size

The entire U.S. talent universe for these titles is smaller than one Intel campus building, which is what makes the Oregon dump so disruptive. In Refolk's index of professional profiles, only 919 U.S.-based people currently hold a Module Development Engineer, Process Integration Engineer, or Module Engineer title. That is the whole country.

Of a top-25 sample from that pool, 16 (64%) work at Intel. TSMC and Apple tied for second at 2 profiles each. The single most common city was Hillsboro, Oregon, with 5 of the top 25. Extrapolated across the 919, Intel employs roughly 588 of the entire U.S. title pool for these roles.

Narrow further to PIEs who list the full photolithography and etch skill stack that leading-edge logic actually requires, and the pool collapses to 44 people nationwide. Intel holds 15 of them (34%). Every other named employer, Applied Materials, IBM, Samsung Austin, Wolfspeed, HRL, MACOM, NIST, and Northrop Grumman, holds exactly one.

44

The important read on this table: the addressable non-Intel PIE bench just tripled overnight. If you are staffing a Phoenix or Malta fab, the market is temporarily on your side.

The absorption math nobody is running

Recruiters expecting a bidding war for these engineers are reading the situation backward. This is a supply shock, so wage compression is more likely than wage inflation for the next 3 to 6 months.

Run the math. Intel just released over 300 module development engineers and a large-but-unstated block of PIEs into a national market that previously held 919 title-holders and only 44 with the deep skill stack. The three realistic buyers, TSMC Arizona, Samsung Austin, and GlobalFoundries Malta, are not simultaneously ramping headcount by hundreds of PIEs each. TSMC Arizona is running an open hiring event, but for technicians, not the sticky module development tier.

Reported average PIE base at Samsung Austin sits around $113,325 (Glassdoor). That is a useful anchor. Intel Oregon compensation for equivalent roles has historically run higher with RSUs and bonus, so candidates should expect a base-comp step down when they relocate to a competing fab. First-mover recruiters win because candidates without severance can't wait out an extended negotiation.

This is a supply shock, not a talent shortage. Wage compression is the base case for the next two quarters.

Why geography, not skill, is the binding constraint

A meaningful share of the 2,392 will exit semiconductors entirely, not because they can't do the work at another fab, but because they can't move. Hillsboro engineers with fixed mortgages and dual-income households don't relocate to Phoenix or Malta on a coin flip.

The KORE1 note is blunt about this: engineers not geographically picky are landing new roles in 2 to 4 weeks. Everyone else is stuck. The realistic outcomes for a Hillsboro-anchored module engineer look like this:

1. Relocate to Phoenix (TSMC), Austin/Taylor (Samsung), or Malta NY (GlobalFoundries). Best comp preservation, hardest life move.
2. Switch to a tool vendor with field or applications engineering roles that can be based in Oregon. Applied Materials, Lam Research, and ASML all have Hillsboro-adjacent field presence. Comp step down, but no move.
3. Exit fab work entirely into adjacent roles where fab expertise is nice-to-have, not core.
4. Wait for Intel to rehire in 12 to 18 months if the foundry business stabilizes. Historically a bad bet during a 31% global headcount reduction.

For sourcing teams, that means the Hillsboro LinkedIn filter alone is misleading. You want to segment by relocation willingness before you run outreach, and the fastest way to do that is a plain-English query rather than 14 nested Boolean filters. This is the exact gap Refolk closes: describe the person you want (open to Phoenix or Austin, module development engineer, ex-Intel Ronler Acres, photolithography and etch stack) and get a ranked shortlist across GitHub, LinkedIn, and the open web without hand-tuning strings.

The four sub-pools, ranked by how fast they clear

Not all 2,392 are the same recruiting problem. Segment them, or you'll waste outreach on candidates who are already gone.

1. Module equipment technicians (over 400): clears in weeks

TSMC Arizona is running open onsite hiring events for exactly this profile. These roles are tool-set-portable (ASML lithography tools, Applied Materials etch, Lam deposition) and the credential is hands-on maintenance experience. If you want any of these techs, be on the ground in Hillsboro within 30 days of WARN close.

2. Manufacturing technicians (unenumerated block): also fast

Similar to above but with less tool specialization. Absorbs into TSMC AZ, Samsung Austin, and any fab-adjacent hardware manufacturer. This tier is not exclusive to leading-edge logic.

3. Module engineers (nearly 150) and module development engineers (over 300): sticky

This is where recipe development on Intel-specific tool configurations creates portability friction. A module dev engineer who spent years tuning EUV recipes on Intel's ASML fleet doesn't slot cleanly into TSMC's process without a multi-month ramp. Buyers know this, which is why comp will compress even though the skill looks rare on paper.

4. Process integration engineers: the strategic pool

The 44-person skilled PIE bench is where the real leverage sits. If you are hiring for advanced-node fab in North America and you don't secure your PIE additions in the next 90 days, you're waiting until the next Intel round to see this supply again. Refolk works well here because the differentiator is a stacked-skill query (advanced node, EUV, high-volume manufacturing, yield ramp) that Boolean strings on LinkedIn cannot express cleanly.

What semiconductor recruiting in Hillsboro looks like from here

Semiconductor recruiting in Hillsboro is now a 90-day sprint against three well-funded competitors and a decaying candidate pool. Move fast or accept that the best of the 2,392 will be sourced by TSMC's in-house team before your kickoff meeting.

The tactical playbook is short:

• Skip the WARN list. Public WARN filings give names and titles late, and they are noisy. Go direct to Hillsboro-tagged LinkedIn and open-web signals.
• Filter by campus, not city. Ronler Acres and Aloha are the specific sub-sites named as the epicenter. Those geo tags help separate fab engineers from design-side roles that survived the cut.
• Prioritize by relocation openness first, skills second. Skills the pool has. Willingness to move to Phoenix or Malta is the actual bottleneck.
• Move on equipment technicians in week one. They clear fastest and are the easiest wins.
• Take 60 days on PIEs. The sticky module engineers deserve careful outreach; the equipment techs don't.

FAQ

How many people did Intel actually cut in Oregon on July 15, 2026?

Intel's revised WARN filing landed at 2,392 workers eliminated in Oregon, expanding an initial November 2025 filing that listed roughly 530 positions. The revised total is about 4.5x the original number and includes more than 400 module equipment technicians, over 300 module development engineers, nearly 150 module engineers, and a large additional block of process integration engineers and manufacturing technicians spread across four Hillsboro-area campuses, including Ronler Acres and Aloha.

Why can only three companies realistically hire these fab engineers?

Advanced-node process integration and module development skills only transfer cleanly to other leading-edge logic fabs, and in the U.S. that list is TSMC Arizona, Samsung Austin/Taylor, and GlobalFoundries Malta. Micron runs memory, Texas Instruments runs analog and mature nodes, and Wolfspeed runs silicon carbide, so none of them need the specific photolithography and etch expertise these engineers have. Apple, Google, and Meta silicon teams hire ex-fab engineers, but into architecture roles, not fab operations.

Should I expect bidding wars for these candidates?

No, expect wage compression for the next 3 to 6 months. Intel released more skilled PIEs onto the market in one action than the entire non-Intel skilled PIE bench previously held (roughly 44 people nationwide, per Refolk's index). With no buyouts cushioning candidates and 60-day WARN windows already closing, most engineers are negotiating from weakness. First-mover recruiters at TSMC Arizona, Samsung Austin, and GlobalFoundries Malta can lock in comp below Intel Oregon totals.

What's the fastest way to source this pool without duplicating the other two fabs' outreach?

Segment by relocation willingness first, then by skill stack, and start with the module equipment technician tier because it clears in weeks. For the sticky module development and PIE tiers, run plain-English queries (ex-Intel Ronler Acres, EUV recipe development, open to Phoenix relocation) rather than trying to encode that logic in LinkedIn Boolean strings. Refolk pulls across GitHub, LinkedIn, and open-web sources in one shot, which matters here because a lot of fab engineers keep thin LinkedIn profiles and richer footprints on patents and conference proceedings.