Intel's Aug 15 WARN: 67 DCAI Engineers in One Santa Clara Building

California WARN filings put a specific date on the next Intel cut: Aug 15, 2026, 103 Bay Area heads, and 67 of them concentrated in one building on Juliette Lane in Santa Clara. If you run AI infrastructure hiring, this is the rare layoff where you can name the building, the org, and the outplacement vendor before a single generalist recruiter figures out what SC-12 even is.

The window between the WARN filing and the day these engineers get sprayed by every agency is short. What follows is what the filing actually says, why SC-12 concentration changes your sourcing approach, and a 10-day playbook.

The cut, in one paragraph

Intel filed a WARN notice to cut 103 Bay Area positions effective Aug 15, 2026, with 67 concentrated at SC-12 (3600 Juliette Lane, Santa Clara) inside the Data Center and AI Group. This is the first quantified glimpse of a DCAI reduction Intel confirmed but never sized. The remaining 36 are split across the Robert Noyce Building HQ, a second Juliette Lane office, and Laurelwood Road. Career transition runs through Lee Hecht Harrison for up to six months. No bumping rights.

This is not a distributed layoff. It is a single-campus event, with the Intel Museum 1,100 feet from SC-12 as a physical anchor.

65%

Why SC-12 concentration changes your sourcing approach

"Ex-Intel" as a LinkedIn filter is the wrong lens when 65% of the cut sits in one building. The right lens is building-level: DCAI engineers who badged into SC-12 recently. Every generalist agency recruiter will run the same "Intel + Santa Clara + Open to work" search on Aug 16 and generate the same mush. You want the 67.

Three practical implications:

• Company filter alone is noise. Intel's global headcount fell from roughly 132,000 in 2022 to about 81,000 today, close to a 40% reduction. The ex-Intel alumni pool is enormous and mostly stale. Aug 15's cohort is a thin, dated slice.
• Building-level signals beat company-level signals. Public bios that mention SC-12, DCAI, or Xeon and Gaudi program work cluster into a much smaller, more relevant set.
• DCAI is the org, not "Intel." The WARN filing is org-specific. Silicon design, verification, SoC architecture, and datacenter platform software are the archetypes. Fab, foundry, and client compute engineers are not on this list.

This is the exact gap Refolk closes: you describe the person in plain English ("Intel DCAI silicon or platform engineer who worked out of SC-12 or Robert Noyce in the last two years, senior IC level") and get a ranked shortlist instead of an alumni dump.

What "DCAI" actually means for the role mix

DCAI is Intel's Data Center and AI Group, the org that ships Xeon server CPUs, Gaudi accelerators, and datacenter platform silicon. Prior Intel California WARN notices flagged design engineers, cloud software workers, and project managers, which is a reasonable prior for the SC-12 role mix on Aug 15. Expect roughly five archetypes:

1. RTL and SoC design engineers working on Xeon or Gaudi generations.
2. Verification engineers on the same programs.
3. Datacenter platform architects and performance engineers.
4. Firmware and low-level software engineers for platform bring-up.
5. Technical program managers attached to those programs.

The important thing about this mix: DCAI revenue grew 22% year over year to $5.05 billion in Q1 2026. Intel is not cutting a shrinking business. Intel is cutting cost structure inside a growing one, which is a very different signal for hiring managers evaluating these resumes.

DCAI grew 22 percent while being cut. That is a cost-structure layoff, not a performance layoff.

The pool this cohort is landing into is tiny

The core U.S. talent pool this cohort competes inside is 743 people, per Refolk's index of the Silicon Design, Verification, SoC, and Datacenter Architect cluster. If the SC-12 role mix mirrors prior WARN disclosures, Aug 15 could displace 5 to 10 percent of that entire national pool in a single day. That is a market-moving event for anyone doing AI infrastructure hiring.

Where those 743 currently work, by top employer, tells you exactly who is winning silicon talent right now:

Microsoft, Apple, NVIDIA, Meta, and Google-adjacent teams hold roughly 80% of the top-hiring seats in this cluster. If you are a Series B AI infrastructure company trying to poach ex-Intel DCAI engineers, that is your comp benchmark and your competitive set. You are not competing with Intel. You are competing with Microsoft Azure silicon and Apple Silicon.

743

Bay Area retention is near-total. Plan accordingly.

Displaced Intel silicon and verification engineers overwhelmingly stay in the Bay Area, so remote-only pitches from Austin or Hillsboro shops will lose to on-site Bay incumbents. Refolk's index shows the cluster's geographic concentration is heavily San Francisco (5), San Jose (2), and Santa Clara (1), with only a thin tail in Hillsboro (1). These engineers own homes here and have watched multiple Intel layoff rounds without leaving the region.

The practical read for hiring managers:

• On-site Santa Clara or Sunnyvale roles win. NVIDIA, Apple, Cerebras, Groq, Tenstorrent, SambaNova, and Microsoft's silicon teams have physical Bay Area presence and will move first.
• Fully remote pitches need a comp premium to overcome the "I already lost my badge, I want a real team again" instinct.
• Hybrid at 2 to 3 days works if the office is south of SFO.

Lee Hecht Harrison is the choke point most sourcers will miss

Every one of the 103 laid-off Intel employees routes through Lee Hecht Harrison for outplacement, up to six months, which makes LHH programming the highest-signal intercept point between Aug 15 and roughly February 2027. Recruiters who show up as speakers, sponsors, or hiring partners meet candidates before those candidates ever post "Open to work."

Three ways to work the LHH channel:

• Sponsor a workshop. LHH regularly places employer partners in front of transitioning cohorts. Even one session in September puts you in front of a meaningful slice of the 103.
• Offer a "no application, one call" track for anyone with an active LHH engagement. Reduces friction dramatically.
• Track LHH alumni signals. Profile updates that shift within the same six-month window as an LHH engagement are your tell.

Combine that with an index query for the exact building and org, and you get a defensible pipeline.

Why this cohort is higher quality than the usual "surplused" profile

DCAI grew 22% year over year to $5.05 billion in Q1 2026, so the Aug 15 cut is a cost-structure decision, not a performance decision. Intel's own line to CRN was that it is aligning the Data Center Group "to ensure the right roles and skills for long-term success," which is corporate-speak for: expenses are too high versus similar-revenue competitors. Lip-Bu Tan is the CEO under whom this round is being executed. That framing has three consequences for the resumes you will see:

1. Skew senior and expensive. Cost-structure cuts pull disproportionately from higher bands.
2. Skew tenured. Long-tenure Intel veterans with deep Xeon or Gaudi context, not new-college hires.
3. Not underperformers. These engineers were on shipping roadmaps in a growing division. That is a rare quality signal on a WARN list, and it is worth saying out loud to your hiring managers when you send the shortlist.

The pitch to a founder or VP Engineering: this is not the usual surplused cohort. This is a 22-percent-growth division shedding cost, and the people on it built silicon currently in datacenter racks.

A 10-day playbook for sourcing ex-Intel engineers from SC-12

The window that matters runs from the WARN filing through roughly Aug 25, before generalist agencies catch up. Here is the sequence:

1. Day 0 to 2. Pull the index list. Query in plain English for Intel DCAI engineers based out of SC-12 or Robert Noyce in the last 24 months. Segment by archetype (RTL, verification, architecture, platform SW, TPM).
2. Day 2 to 4. Warm the LHH channel. Reach out to LHH's Bay Area career transition team. Offer to run a session in September.
3. Day 4 to 7. First-touch outreach. Reference SC-12 explicitly. Do not say "ex-Intel." Say "DCAI" or "Xeon" or "Gaudi." Specificity is the signal.
4. Day 7 to 10. Book calls before Aug 15. The best candidates will have offers within 21 days of separation.
5. Post Aug 15. Track profile changes daily.

The specificity is the whole game. "Ex-Intel" is a tens-of-thousands-person query. "DCAI verification engineer, SC-12, senior IC" is a small, addressable one. The Intel Santa Clara WARN notice tells you exactly which query to run.

FAQ

How do I identify which engineers are actually on the Aug 15 WARN list?

You cannot get the names from the filing itself. What you can do is match role archetypes and building signals: DCAI, SC-12 or Robert Noyce, senior IC, silicon or platform focus. Refolk's index lets you describe that composite in plain English and returns a ranked shortlist. Cross-reference with LHH engagement signals starting mid-August and you close the loop.

What comp should I offer to be competitive?

Benchmark against Microsoft Azure silicon, Apple Silicon, and NVIDIA datacenter teams, not against Intel's internal bands. Microsoft, Apple, NVIDIA, Meta, and Google-adjacent teams hold roughly 80% of top-hiring seats in this cluster per Refolk's index, and they set the market. If you are a scale-up like Groq, Cerebras, or Tenstorrent, expect to match total comp and lean on equity upside and technical scope.

Is this cohort worth the effort if it is only 67 people?

Yes, because the addressable U.S. pool for this exact archetype is only 743 people. The Aug 15 SC-12 cohort could be 5 to 10 percent of that entire national pool, concentrated in one building, on one date, with one outplacement vendor. There is no other event this year that hands you this much precision.

Should I also chase the 24 at the Robert Noyce Building?

Yes, but expect a different mix. Robert Noyce is HQ, so the 24-person cut skews toward program management and staff functions rather than core silicon design. If your open reqs are director-level datacenter platform or GM-track roles, the RNB list is more relevant than SC-12. If you are hiring ICs, SC-12 is where 67 of the 103 sit and where you should spend 80% of your time.