Etched Raised $300M to Hardcode Transformers. The US Pool Is 7.
Etched's $10.3B Series C bets on transformer-hardcoded silicon. The US engineers who can build it number 7, not 74. Here is how to find them.
On July 23, 2026, Etched closed a $300M Series C at a $10.3B valuation, the largest Series C check Sequoia has ever written. The company now sits at roughly 400 employees and is hiring across "inference, firmware, platform, chip design." That last bucket, chip design, is where the labor market breaks: the engineers who can hardcode transformer attention into silicon almost do not exist.
Why Etched's raise is really a labor story
Etched raised $300M to buy engineers, not fabs. Sohu, Etched's ASIC, fabricated on TSMC's 4nm node, has one job: run transformer inference. There are no general-purpose compute paths and no fallback modes. The transformer architecture is hardcoded into the silicon, which means the RTL engineers building it need to understand attention math at a level GPU architects almost never do.
The round doubled Etched's valuation from the roughly $5B mark it reached in a $500M round led by Stripes in late 2025. a16z, Jane Street, SK Hynix, and Diffusion joined. Total funding is past $1B. There is a 10-megawatt new product introduction lab operational in Milpitas, California, an 80,000 sq ft facility scaling production, and a Taiwan factory. Andrej Karpathy is an angel, a useful credibility signal on the transformer-permanence thesis the whole company is built on.
Sohu's claim: an eight-chip server hits over 500,000 tokens per second on Llama 70B, versus roughly 23,000 to 25,000 on an eight-H100 setup. That is a ~20x throughput number that has not been independently verified, and Etched has not published batch-size numbers at production scale. The company also claims Sohu can replace 160 H100s for inference tasks, and it emerged from stealth with over $1B in signed customer contracts. Investors are not underwriting the benchmark. They are underwriting the bet that no one else can copy this quickly, because no one else can hire the people.
The pool is 7, not 74
The realistic US pool of engineers who can build Sohu-class silicon is 7, not 74. In Refolk's index of professional profiles, 22,188 senior-plus engineers in the US carry Verilog as a skill. Add "inference accelerator" as a headline keyword and the number collapses to 7. Add "transformer attention" as a headline keyword and it collapses to zero, because the labor market's vocabulary simply does not include that string in job titles.
That is a 0.032% intersection, or roughly one transformer-aware RTL specialist per 3,170 senior Verilog engineers. At roughly 400 employees, Etched has plausibly already absorbed a meaningful fraction of the entire addressable US intersection. Any competitor (MatX, Rain, Taalas, Positron) is fishing in a puddle. The real fundraise was labor, not silicon.
| Segment (US, current employment) | Count | Note |
|---|---|---|
| Senior+ engineers with Verilog skill | 22,188 | The raw RTL denominator |
| Verilog + "inference accelerator" headline | 7 | The actionable intersection |
| Verilog + "transformer attention" headline | 0 | The string does not exist in titles |
| Intersection as % of RTL denominator | 0.032% | Derived (7 / 22,188) |
| RTL engineers per transformer-aware specialist | ~3,170 | Derived multiple |
| Top employers of the intersection cohort | AWS, Meta, Microsoft, Intel, d-Matrix | Where the 7 actually work |
Regional concentration of those 7: two in the San Francisco Bay Area, one in Austin, one in the Detroit metro, and the rest scattered. Milpitas HQ sits inside the densest cluster, which is a real advantage on onsite closes.
Why Nvidia, Cerebras, and Groq don't map cleanly
Ex-Nvidia, ex-Cerebras, and ex-Groq engineers do not port to Etched cleanly, and the reason is mechanical, not cultural. GPU and wafer-scale architects design programmable datapaths. Hardcoding attention means fixing dataflow, tiling, and numerics at the RTL level and never changing them. Those are different jobs.
- Nvidia SM architects design streaming multiprocessors that must run any CUDA kernel. That flexibility is exactly what Sohu throws away.
- Cerebras wafer-scale architects think about fabric and yield at extreme scale, but the compute tiles remain general-purpose.
- Groq LPU architects understand fixed-function AI dataflow, which is closer, but Groq's chip is not transformer-hardcoded. The compiler carries the specialization.
The cleanest match is the ex-Google TPU MXU team, the group that designed a matmul-fixed unit for one workload. That is a much smaller pool, in the low dozens, and it is where MatX (founded by ex-Google TPU engineers Reiner Pope and Mike Gunter) already fished. Etched will fish there too, alongside Meta's MTIA team and AWS's Trainium/Inferentia team, both of which appeared in Refolk's intersection top companies.
Etched's real fundraise was labor. The silicon is downstream of a hiring moat competitors cannot cross with capital alone.
Boolean title search is worthless here
LinkedIn title search will return nothing useful for this role, because the vocabulary does not exist in headlines. Zero US senior Verilog engineers put "transformer attention" in their title. Sourcers who lead with Boolean strings against title: fields will spend a week and find nobody.
The signal lives elsewhere:
- GitHub commits to accelerator repos. Contributors to FlashAttention CUDA/PTX kernels,
tenstorrent/tt-metal, and ROCm composable kernel work carry the exact skill combination even when their LinkedIn says "ASIC Design Engineer II." - Patents. USPTO filings assigned to Google (TPU MXU), Meta (MTIA), and AWS (Trainium) that name attention, systolic arrays, or KV-cache handling identify the people who have actually shipped this work.
- Conference proceedings. ISSCC, HotChips, MICRO, and ISCA papers on transformer accelerators are a public roster of exactly the humans Etched needs.
- Project descriptions on LinkedIn. Not headlines. The word "attention" or "GEMM tiling for LLM inference" tends to sit three paragraphs deep in a job description, invisible to title-only search.
This is the exact gap Refolk closes for hardware sourcing: you describe the person in plain English ("senior Verilog engineer in the US who has worked on inference accelerators or transformer hardware, ideally with GitHub activity on tt-metal or FlashAttention"), and Refolk ranks the shortlist across LinkedIn, GitHub, and the open web instead of forcing you to reverse-engineer a Boolean.
Prefill and decode are two different hires
Etched's architecture forces two distinct hiring specs, not one. The company splits inference into its two natural phases: a low-voltage prefill chip, and a cluster-scale memory system that lets many chips pool memory for decode. Sourcers who treat "chip design" as a single bucket will bring in the wrong second candidate every time.
Prefill: compute-bound
Prefill runs the initial context pass. It is compute-bound and physical-design-heavy.
- Systolic-array design experience (Google TPU MXU, Tesla Dojo, or startup equivalents).
- Low-voltage physical design and power-aware floorplanning.
- Numerics work: FP8, MX formats, block-scaled quantization for attention and MLP layers.
- Comfort fixing dataflow at RTL rather than in a compiler.
Decode: memory-bound
Decode generates tokens one at a time. It is memory-bound and interconnect-heavy.
- HBM controller design (HBM3E and beyond).
- Cluster-scale network-on-chip design and coherence protocols.
- KV-cache-aware fabric design, which barely exists as a discipline outside the hyperscaler in-house teams.
- Experience with disaggregated memory systems.
The overlap between "great systolic-array designer" and "great HBM/NoC architect" is small. When you brief a sourcer, split the JD.
Where to actually raid
The intersection cohort clusters at six companies, and each requires a different pitch. Refolk's index shows the top employers among the 7 as AWS, Meta, Microsoft, Intel, and d-Matrix, with the broader senior Verilog cohort skewing to OpenAI (3), NVIDIA (2), and NXP (2) at the top.
| Company | Why they're on the list | Realistic pitch to Etched |
|---|---|---|
| AWS Trainium/Inferentia | In-house transformer-aware RTL at scale | Ownership over a whole datapath, not a subteam |
| Meta MTIA | Purpose-built AI accelerator team | Ship on a shorter cycle than Meta's internal roadmap |
| d-Matrix (Santa Clara) | Digital in-memory compute, closest cultural analog | Same thesis, earlier equity |
Tenstorrent (tt-metal contributors) | Public open-source signal of transformer-aware HW skill | Move from open-source flexibility to a hardcoded bet |
| MatX | Ex-Google TPU DNA | Direct competitor; only movable on mission or comp |
| Groq | Fixed-function AI dataflow experience | Retrain onto RTL-fixed attention rather than compiler-fixed |
OpenAI's hardware team, three senior Verilog engineers deep per Refolk's index, is the quiet raid target most people miss. OpenAI has not shipped custom silicon publicly, which means the work is greenfield and the equity is uncertain compared to a $1B-funded company shipping chips.
What this means for your outbound
Rewrite the message. A generic "senior ASIC role, competitive comp, hot AI company" note will not move an engineer already sitting on Meta or AWS equity doing the same work internally. Three signals actually pull replies from this cohort:
- Specificity about the block. Name the datapath. "We're staffing the decode-side KV-cache fabric, reporting to [named tech lead]" beats "chip design role" by an order of magnitude.
- Architectural credibility. Reference the prefill/decode split, the 4nm node, and the fact that Karpathy is an angel. This cohort screens for whether the recruiter understands the chip.
- A defensible answer on obsolescence risk. The core risk of Sohu is that a successor architecture replaces transformers at scale. Any candidate senior enough to be worth top-of-market comp will ask about this. Have the answer ready: which fixed-function blocks are transformer-generic (matmul, softmax, layernorm) and which are attention-specific.
FAQ
How many US engineers can actually build a transformer-hardcoded ASIC?
Roughly 7, based on Refolk's index of senior US Verilog engineers who also carry "inference accelerator" as a headline keyword. The broader denominator is 22,188 senior Verilog engineers in the US, which means the intersection is about 0.032%, or one specialist per 3,170 RTL engineers. The number may be slightly higher when you add non-headline signals like patents and GitHub commits, but it is closer to double digits than triple.
Why don't ex-Nvidia engineers count?
Nvidia SM architects design programmable datapaths. Etched's Sohu chip throws programmability away and fixes dataflow, tiling, and numerics for one architecture in RTL. Ex-Nvidia engineers can retrain onto this work, and some will, but they are not drop-in hires. The cleanest match is the ex-Google TPU MXU team, which already designed a matmul-fixed unit for one workload, and secondarily Meta MTIA and AWS Trainium/Inferentia engineers.
Is Etched's 20x throughput claim real?
Etched claims an eight-chip Sohu server hits over 500,000 tokens per second on Llama 70B, versus 23,000 to 25,000 for an eight-H100 setup, and that Sohu can replace 160 H100s for inference. Those figures have not been independently verified, and Etched has not published batch-size numbers at production scale. Investors underwrote the labor moat and the $1B in signed customer contracts, not the benchmark.
What's the single best sourcing signal for this role?
GitHub contribution history on accelerator repos, especially tenstorrent/tt-metal, FlashAttention CUDA/PTX kernels, and ROCm composable kernels, cross-referenced with a senior Verilog skill on LinkedIn. Patents assigned to Google, Meta, or AWS that name attention or systolic arrays are the second signal. Job titles are the worst signal in the entire stack for this search.