Cisco's 75% Placement Clock: Source the Acacia and Silicon One Leavers First
Cisco cut under 4,000 on May 13 to fund silicon, optics, and AI. The hardware-side window closes in weeks. Here's how to source it.
On May 13, 2026, Cisco announced it would cut fewer than 4,000 roles, less than 5% of an 86,200-person workforce, on the same call it reported a record Q3 and raised full-year AI infrastructure orders to $9 billion. Notifications started May 14. If you are sourcing networking engineers off this news, you are about to waste two weeks chasing the wrong list.
The prize here is not "ex-Cisco." The prize is the narrow hardware slice (silicon, optics, ASIC, photonics) that Cisco is simultaneously funding and reshuffling, and that Cisco's own internal placement program (historical 75% success rate) will quietly reabsorb if you move slowly.
The cut is a reallocation, not a retreat
CFO Mark Patterson said the quiet part on the earnings call: this "was really not a savings-driven restructure," it was "realigning resources around silicon, optics, security and AI." Read the press release the same way. The capital from those 4,000 roles is being redirected into Silicon One, Acacia, the Splunk-era security stack, and internal AI tooling.
The math backs the language. Cisco has taken $5.3 billion in AI infrastructure orders from hyperscalers this fiscal year, raised the full-year target to $9 billion, and Patterson projected at least $6 billion of AI hyperscale revenue recognition in fiscal 2027. Total product orders are up 35% year-over-year. The restructuring plan itself will cost up to $1 billion, with $450 million booked in Q4 and the rest in fiscal 2027. That is a company buying optionality, not trimming for survival.
Which means most of the 4,000 are not who you want. The "reducing roles in some areas" language plus the explicit silicon/optics/security/AI carve-out points at sales ops, services, post-Splunk security duplication, legacy Webex and collab, and back-office. A keyword blast on "ex-Cisco" gets you mostly those profiles. The hardware-side leavers are a different cohort, in different zip codes, with very different alternatives.
Where the real talent sits
Two physical nodes matter most.
San Jose is where the Silicon One ASIC team lives. Silicon One (the G100, and the newer G200) is Cisco's in-house networking ASIC line. Microsoft was an early adopter. Meta has announced plans to deploy the Cisco 8501, which pairs the Silicon One G200 with a Cisco-designed system. The engineers who tape out those chips are precisely the people Patterson's "realignment" is supposed to protect, so the ones who leave will skew toward people who actively want out of big-company networking.
Maynard, Massachusetts is Acacia Communications, Cisco's coherent and silicon-photonics group. Acacia is the crown jewel for shrinking complex, power-hungry optical systems into pluggable form factors that hyperscalers buy by the rack. It is specifically named in Cisco's growth narrative. Anyone walking out of Acacia this month is the highest-leverage target on your desk.
A third, smaller node is RTP and Boxborough, where some networking and platform engineering still concentrates.
This is unusually tight geography. A recruiter who shows up physically (coffee in Maynard, Optical Society alumni meetups, the IEEE photonics circuit in the Bay) will out-source anyone running LinkedIn keyword pings from a different time zone.
The 75% placement clock is the real deadline
Cisco's outplacement program, paired with a year of Cisco U access and certification credits, has historically helped about 75% of participants land their next role. That number is the countdown clock, not the WARN notice. It works two ways against outside recruiters:
- A meaningful share of strong hardware ICs will be quietly rehired into the same silicon and optics teams Cisco is funding. Internal transfer is the path of least resistance, especially for ASIC engineers whose families do not want to move.
- The rest get picked off fast by direct competitors who already know them by name.
The Cisco placement program window for external sourcing is measured in weeks, not the 60 days you might assume from a typical WARN cycle. By the time most ATS-driven recruiters finish enriching their "Cisco" list in July, the hardware cohort will be gone.
The hardware-side leavers are not a list you can buy. They are a list you have to describe. </pull> This is exactly the friction we built [Refolk](/) to remove. Instead of buying an "ex-Cisco" CSV and filtering down, you describe the person ("senior ASIC physical design engineer, 8+ years, Silicon One or comparable, currently in San Jose, open in the next 30 days") and get a ranked shortlist across GitHub, LinkedIn, and the open web. The keyword filter on a job board cannot tell Silicon One from Webex. A plain-English query can.
refolk prompt: Senior silicon photonics or coherent DSP engineers within 30 miles of Maynard MA, 5+ years at Acacia, Lumentum, Coherent, or Ayar Labs, open to startups note: You get a ranked shortlist of the Acacia-adjacent optics ICs most likely to move, with current employer, tenure, and reachable contact paths, not a thousand "networking engineer" near-misses. slug: 464eqkj1qy
## Who else is fishing in this pond
If you do not have a credible competing offer, you are wasting your warm intros. The named hardware-side competitors hiring this cohort right now:
- **Broadcom** (silicon photonics PIC design)
- **Marvell** (Santa Clara, advanced photonics)
- **Nokia** (silicon photonics design)
- **Apple** (Cupertino, biophotonics and silicon validation)
- **Intel Hillsboro** (silicon design)
- **Lumentum, Coherent, Mitsubishi, Sumitomo** (the EML supply base, supply-constrained because NVIDIA has pre-allocated capacity past 2027)
And the startup pull, where ex-Cisco hardware engineers actually want to land if they leave at all:
- **Ayar Labs** (San Jose, co-packaged optics, backed by AMD, Intel, and NVIDIA)
- **Lightmatter** ($4.4B valuation, Passage M1000)
- **HyperLight** (Cambridge MA, thin-film lithium niobate photonics)
Note who is missing from your "competition" list: generic networking vendors. Juniper, Arista, even hyperscaler networking teams that are not buying Silicon One are not the threat. The threat is the customer relationships these engineers already have. Microsoft and Meta are publicly named Silicon One customers. Meta is the #1 employer of senior optical and ASIC engineers in our index. The people most likely to hire an exiting Silicon One engineer are the people who already sat in their design reviews.
## The supply picture justifies the urgency
Even before May 13, the senior hardware market was structurally short. Industry data suggests vacancy rates for senior IC design roles could reach 35% by mid-2026. Average time-to-fill for a senior hardware engineering role is 94 days versus 58 for software. Forty percent of Principal IC Design and Verification Architect roles sit unfilled after six months.
Layer on NVIDIA's pre-allocation at the top EML suppliers (Lumentum, Coherent, Mitsubishi, Sumitomo, Broadcom), which has pushed optical component lead times past 2027 and triggered a real supply shortage. That shortage translates one-to-one into a talent squeeze. Anyone in the EML or coherent stack with five years of relevant tape-outs is already getting inbound. After May 14, they are getting two more a day.
How to actually run the next 21 days
A few things I would do this week if I were running sourcing for a photonics startup or a hyperscaler in-house silicon team.
1. Stop pulling lists by company. Start pulling by signal.
"Ex-Cisco" is a 4,000-name haystack with maybe 200 needles. You want the needles: ASIC physical design, DFT, place-and-route at advanced nodes, silicon photonics PIC layout, coherent DSP, optical packaging, foundry liaison. This is where AI infrastructure hiring lives or dies. When sourcing silicon and optics talent specifically, the right filter is project history (Silicon One G100/G200 work, Acacia CIM modules, specific tape-outs) which lives in GitHub commits, conference papers, and patent filings, not in titles.
This is a place Refolk earns its seat: querying the open web for "engineers credited on Silicon One G200 papers or patents who are not currently posting Cisco in their headline" surfaces people no LinkedIn search will catch.
2. Lead with a story, not comp.
Cisco severance plus one year of placement support and certifications means these candidates are not desperate. Severance and transition cash is real. A recruiter pitching "we pay X" is competing against Meta, which pays X plus the relationship. Pitch the alternative: a startup with shipping silicon, a hyperscaler team that is not also their former customer, or a problem (co-packaged optics, TFLN, photonic interconnect) they cannot work on inside Cisco.
3. Work Maynard in person.
There are maybe 150 Acacia engineers who matter. They all know each other. One credible warm intro in Maynard is worth a thousand InMails. If you cannot fly, find the local IEEE Photonics chapter calendar and sponsor coffee.
4. Skip the boomerang trap.
A meaningful share of the people you reach will be in active conversations to transfer internally to Silicon One or Acacia. If a candidate hesitates about Cisco severance details on the first call, they are not in the market. Move on. Your time-boxed window does not have room for tire-kickers who will reabsorb in 30 days.
5. Build the second list now.
The Cisco event is one of three or four hardware-side dislocations queued up this year between hyperscaler in-house silicon programs ramping and the EML supply crunch. Use the next three weeks to build relationships, not just close reqs. The same people you talk to in May about Silicon One will be the people you call in September when the next photonics startup blows up.
The bottom line
Cisco's May 13 move is being read as a layoff story. It is closer to a hiring story dressed in layoff clothes. The company is shedding generic networking and back-office to fund more silicon, optics, security, and AI tooling, and its 75% placement program will quietly recover most of the hardware-side losses internally. The externally-available silicon and optics talent is a small, geographically concentrated, time-boxed cohort that hyperscalers and photonics startups are already moving on.
Source the hardware side. Source it this week. And source it by describing the person, not by buying the list.
FAQ
How many of the ~4,000 Cisco layoffs are actually silicon or optics engineers?
Almost none, in proportional terms. Cisco explicitly carved out silicon, optics, security, and AI as investment areas, and Patterson framed the cut as a realignment, not savings. The 4,000 skews toward sales ops, services, legacy collaboration and Webex, post-Splunk security duplication, and back-office. The hardware-side leavers are a much smaller subset, likely in the low hundreds across Silicon One in San Jose, Acacia in Maynard, and platform engineering in RTP and Boxborough. That is the cohort worth running a sourcing sprint on.
What does Cisco's 75% placement success rate mean for my window?
It means a large share of strong ICs will be reabsorbed (either internally into the silicon and optics teams Cisco is funding, or externally by competitors and customers who already know them) within weeks. Cisco's outplacement plus one year of Cisco U credits is real, capable, and fast. By the time most outside recruiters finish enriching their post-WARN lists, the hardware cohort will be gone. Plan for a 2 to 4 week effective window, not 60 days.
Who is competing for ex-Cisco silicon and optics engineers?
For ASIC and silicon: Broadcom, Marvell, Apple, Intel Hillsboro, Nvidia in-house silicon, plus Microsoft and Meta who are existing Silicon One customers. For optics and photonics: Lumentum, Coherent, Nokia, Mitsubishi and Sumitomo on the supply side, and Ayar Labs, Lightmatter, and HyperLight on the startup side. If you are not on that list and cannot tell a credible alternative story (mission, problem space, equity terms), you are unlikely to win heads-up bids.
How should I search for these candidates if not by "ex-Cisco"?
By signal, not by company. The right inputs are tape-out history at advanced nodes, named involvement in Silicon One G100 or G200, Acacia coherent modules, conference papers (OFC, ISSCC, JLT), patent filings, and current geography. That information lives across GitHub, LinkedIn, patent databases, and conference proceedings, not in any one tool's filter UI. A plain-English query through Refolk that says what the person did, not where they worked, is the fastest way to get from "Cisco layoffs 2026" headlines to a ranked shortlist you can actually call this afternoon.