Design and Verification Engineer

About ChipAgents

ChipAgents is reinventing semiconductor design and verification through agentic AI workflows. Founded by leading experts in AI and chip design, we work with top-20 semiconductor companies, major cloud providers, and next-generation hardware startups. Our AI-powered platform accelerates RTL design, verification, and simulation, enabling engineers to achieve unprecedented productivity and correctness.

Position Overview

We are seeking a highly capable Design and Verification Engineer to join our core product and research team. In this role, you will work side-by-side with our AI engineering and research groups to build cutting-edge agentic AI systems for EDA. Your deep domain expertise in RTL design and functional verification will shape how AI systems reason about complex hardware workflows - from architecture specification through testbench validation. You will play a central role in teaching our AI how engineers think and work, ensuring our solutions integrate naturally into real-world design environments.

Key Responsibilities

• Collaborate with AI engineers to model and codify chip design and verification workflows.

• Design, implement, and debug RTL designs and SystemVerilog/UVM testbenches used in training and validating AI agents.

• Provide deep domain expertise to help AI agents interpret specifications, generate RTL code, and understand verification coverage.

• Build reusable examples, design patterns, and edge cases to train and evaluate generative and agentic AI models.

• Support benchmarking and evaluation of AI-assisted design and verification productivity across realistic chip development tasks.

• Work closely with customers, product, and research teams to translate engineering pain points into automated AI workflows.
  

Qualifications

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related field.

• Experience in RTL design, functional verification, and/or architecture-level modeling.

• Proficiency with Verilog/SystemVerilog, UVM, and simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa).

• Experience designing and verifying complex subsystems or SoCs, preferably in production or research tapeouts.

• Familiarity with lint, CDC, formal, coverage analysis, and synthesis flows.

• Interest or experience in AI/ML, especially AI-assisted engineering tools, is a major plus.

• Strong collaboration skills and a passion for enabling the next generation of EDA workflows.
  

Why Join Us

• Work at the frontier of AI and semiconductor design.

• Collaborate with a world-class team spanning AI, systems, and EDA.

• Shape a foundational shift in how chips are built.
  

What we offer

• $150K/yr - $350K/yr + Offers Equity. We are open to discuss above-scale compensation with exceptional candidates on a case-by-case basis.

• Unlimited PTO and full benefits (medical, vision, dental, 401k).

• Two engineering-centric offices with free parking, private gym, and free lunch, drinks and snacks.